The present invention relates generally to a semiconductor memory, and more particularly to a memory chip package with efficient data I/O control.
Size and weight of electronic devices are getting smaller and lighter in line with the technological developments in the semiconductor industry in response to the customer needs. One technique for meeting such needs is the multi-chip packaging technique. The multi-chip packaging technique as implied by the name is a technique for forming a package having a plurality of semiconductor chips within it. Use of a multi-chip package provides advantages in terms of smaller size, lighter weight, and the reduced mounting area as compared to use of several packages each having one semiconductor chip.
The size of a memory cell of a nonvolatile memory device (i.e., a memory chip built in the package), which is implemented to store a large amount of information, is being reduced. With reduction in size of the memory cell, the number of memory cells which are simultaneously programmed through a single program operation is increased. If the number of memory cells that can be simultaneously programmed were to increase and if the number of memory chips that can be simultaneously programmed were also to increase, then these will lead to improvement in the program performance.
A memory chip package includes peripheral circuits for controlling the memory chips and performing a data input and output (I/O). The peripheral circuits can include, for example, a controller coupled to the memory chips and configured to enable the memory chips, issue operation commands, or control the data I/O and an I/O pad circuit for commands or data inputted to and output from the memory chips.